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The University of Southampton
University of Southampton Malaysia

Energy efficient many-core processor architectures Seminar

Time:
16:00 - 17:00
Date:
10 December 2014
Venue:
Lecture Theatre Room 1019

Event details

The traditional approach to boosting efficiency of microprocessors through architectural specialization and increasingly complex full custom design has led to ever increasing design and verification costs, increasing lead times, and increasing energy consumption.

These issues have now become critical as they hinder further developments in the overall full-custom design approach to high-performance processing.  A fundamentally different approach is needed, for example, to utilize clusters of small embedded processors that can successfully address the cost and energy issues. Approaches based on using many-core embedded processors promise substantial gains in energy efficiency by eliminating the complexity of a high-speed microprocessor and facilitating substantial reductions in wasted opcodes, wasted bandwidth, and wasted energy. Moreover, parallelization of time-demanding tasks can allow slower clock speeds which, coupled with reductions in the supply voltage to the near-threshold and sub-threshold levels, can lead to further energy savings.  The many-core approach opens new possibilities of hardware-software trade-offs and tuning as it establishes a link between the application programmer and hardware design engineer. Such a link enables efficient simultaneous software optimization and semi-specialized processor hardware design. Powerful FPGA platforms, which appeared in recent years, make such software-hardware co-tuning fast and cost effective since the design is verified and tested before a full-custom many-core implementation is attempted.

The talk will give examples of very recent developments in energy-efficient multi-core processor design which demonstrate that the processor architecture development has taken a radically new direction. It will also address the trade-offs between energy consumption and performance and will give examples of different leading-edge many-core platforms optimised for energy consumption.

Speaker information

Dr. Tom J Kazmierski ,received the M.S. degree in Electronic Engineering from the Warsaw University of Technology, Warsaw, Poland, in 1973 and the Ph.D. degree from the Military University of Technology, Warsaw, in 1976. Currently he is a Senior Lecturer in the School of Electronics and Computer Science, University of Southampton, Southampton, U.K., where he pursues research into numerical modelling, simulation, and synthesis techniques for computer-aided design of very large scale integration (VLSI) circuits and mixed-technology systems.

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