Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedThu Jul 30 15:59:15 2015 product_versionVivado v2015.2 (64-bit)
build_version1266856 os_platformWIN64
registration_id175615891_134688_210578762_126 tool_flowVivado
betaFALSE route_designTRUE
target_familyzynq target_devicexc7z010
target_packageclg400 target_speed-1
random_id02ae900cd52a5ab3a0d49da5c365a7f4 project_idc8575f642a17485ab00df03dad987bf5
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-3720QM CPU @ 2.60GHz cpu_speed2591 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=2 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1 board=Zybo

unisim_transformation
pre_unisim_transformation
bibuf=130 bufg=1 carry4=54 fdre=2033
fdse=147 gnd=103 ibuf=8 lut1=233
lut2=380 lut3=737 lut4=298 lut5=379
lut6=806 obuf=4 ps7=1 ramb36e1=2
srl16e=31 srlc32e=105 vcc=91
post_unisim_transformation
bibuf=130 bufg=1 carry4=54 fdre=2033
fdse=147 gnd=103 ibuf=8 lut1=233
lut2=380 lut3=737 lut4=298 lut5=379
lut6=806 obuf=4 ps7=1 ramb36e1=2
srl16e=31 srlc32e=105 vcc=91

placer
usage
lut=1942 ff=1740 bram36=2 bram18=0
ctrls=99 dsp=0 iob=12 bufg=0
global_clocks=1 pll=0 bufr=0 nets=8158
movable_instances=4570 pins=26986 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=7.150000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=1740 srls_augmented=0
srls_newly_gated=0 srls_total=136 bram_ports_augmented=0 bram_ports_newly_gated=0
bram_ports_total=4 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
IP_Integrator/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=BlockDiagram
x_ipname=system x_ipversion=1.00.a x_iplanguage=VHDL numblks=18
numreposblks=12 numnonxlnxblks=0 numhierblks=6 maxhierdepth=0
da_axi4_cnt=3 da_board_cnt=1 da_bram_cntlr_cnt=1 da_ps7_cnt=1
synth_mode=Global
axi_bram_ctrl/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_bram_ctrl x_ipversion=4.0 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_bram_inst_mode=EXTERNAL c_memory_depth=2048 c_bram_addr_width=11
c_s_axi_addr_width=13 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4
c_s_axi_supports_narrow_burst=0 c_single_port_bram=1 c_family=zynq c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ecc=0 c_ecc_type=0 c_fault_inject=0
c_ecc_onoff_reset_value=0
axi_crossbar_v2_1_axi_crossbar/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_num_slave_slots=1 c_num_master_slots=4
c_axi_id_width=12 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=0
c_num_addr_ranges=1 c_m_axi_base_addr=0x00000000400000000000000043c0000000000000412100000000000041200000 c_m_axi_addr_width=0x0000000d000000100000001000000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x0000000c c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x00000001000000010000000100000001
c_m_axi_read_connectivity=0x00000001000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x00000001000000010000000100000001 c_m_axi_read_issuing=0x00000001000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x00000000000000000000000000000000 c_connectivity_mode=0
axi_gpio/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=4 c_gpio2_width=32 c_all_inputs=1 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=0 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=4 c_gpio2_width=32 c_all_inputs=1 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=0 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_protocol_converter_v2_1_axi_protocol_converter/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=0
c_ignore_id=1 c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=0
c_ignore_id=1 c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/3
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=2 c_s_axi_protocol=0
c_ignore_id=1 c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
axi_protocol_converter_v2_1_axi_protocol_converter/4
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_protocol_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_m_axi_protocol=0 c_s_axi_protocol=1
c_ignore_id=0 c_axi_id_width=12 c_axi_addr_width=32 c_axi_data_width=32
c_axi_supports_write=1 c_axi_supports_read=1 c_axi_supports_user_signals=0 c_axi_awuser_width=1
c_axi_aruser_width=1 c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1
c_translation_mode=2
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_xdevicefamily=zynq c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=0 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=NONE c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=2048 c_read_depth_a=2048 c_addra_width=32 c_has_rstb=0
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=0
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=2048 c_read_depth_b=2048
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=2 c_count_18k_bram=0
c_est_power_summary=Estimated Power for IP _ 5.3746 mW
led_ip_v1_0/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=XUP
x_ipname=led_ip x_ipversion=1.0 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED led_width=4 c_s_axi_data_width=32 c_s_axi_addr_width=4
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=zynq c_ext_rst_width=4 c_aux_rst_width=4
c_ext_reset_high=0 c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1
c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
processing_system7_v5.5_user_configuration/1
iptotal=1 pcw_uiparam_ddr_freq_mhz=525 pcw_uiparam_ddr_bank_addr_count=3 pcw_uiparam_ddr_row_addr_count=14
pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_cwl=6 pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_t_rc=48.75 pcw_uiparam_ddr_t_ras_min=35.0 pcw_uiparam_ddr_t_faw=40.0
pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_dqs_to_clk_delay_0=-0.073 pcw_uiparam_ddr_dqs_to_clk_delay_1=-0.034 pcw_uiparam_ddr_dqs_to_clk_delay_2=-0.03
pcw_uiparam_ddr_dqs_to_clk_delay_3=-0.082 pcw_uiparam_ddr_board_delay0=0.176 pcw_uiparam_ddr_board_delay1=0.159 pcw_uiparam_ddr_board_delay2=0.162
pcw_uiparam_ddr_board_delay3=0.187 pcw_uiparam_ddr_dqs_0_length_mm=0 pcw_uiparam_ddr_dqs_1_length_mm=0 pcw_uiparam_ddr_dqs_2_length_mm=0
pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dq_0_length_mm=0 pcw_uiparam_ddr_dq_1_length_mm=0 pcw_uiparam_ddr_dq_2_length_mm=0
pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_clock_0_length_mm=0 pcw_uiparam_ddr_clock_1_length_mm=0 pcw_uiparam_ddr_clock_2_length_mm=0
pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_dqs_0_package_length=101.239 pcw_uiparam_ddr_dqs_1_package_length=79.5025 pcw_uiparam_ddr_dqs_2_package_length=60.536
pcw_uiparam_ddr_dqs_3_package_length=71.7715 pcw_uiparam_ddr_dq_0_package_length=104.5365 pcw_uiparam_ddr_dq_1_package_length=70.676 pcw_uiparam_ddr_dq_2_package_length=59.1615
pcw_uiparam_ddr_dq_3_package_length=81.319 pcw_uiparam_ddr_clock_0_package_length=54.563 pcw_uiparam_ddr_clock_1_package_length=54.563 pcw_uiparam_ddr_clock_2_package_length=54.563
pcw_uiparam_ddr_clock_3_package_length=54.563 pcw_uiparam_ddr_dqs_0_propogation_delay=160 pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dq_0_propogation_delay=160 pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_clock_0_propogation_delay=160 pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_crystal_peripheral_freqmhz=50.000000 pcw_apu_peripheral_freqmhz=650 pcw_dci_peripheral_freqmhz=10.159
pcw_qspi_peripheral_freqmhz=200 pcw_smc_peripheral_freqmhz=100 pcw_usb0_peripheral_freqmhz=60 pcw_usb1_peripheral_freqmhz=60
pcw_sdio_peripheral_freqmhz=50 pcw_uart_peripheral_freqmhz=100 pcw_spi_peripheral_freqmhz=166.666666 pcw_can_peripheral_freqmhz=100
pcw_can0_peripheral_freqmhz=-1 pcw_can1_peripheral_freqmhz=-1 pcw_wdt_peripheral_freqmhz=133.333333 pcw_ttc_peripheral_freqmhz=50
pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_freqmhz=133.333333 pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_clk0_peripheral_freqmhz=133.333333
pcw_ttc1_clk1_peripheral_freqmhz=133.333333 pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_pcap_peripheral_freqmhz=200 pcw_tpiu_peripheral_freqmhz=200
pcw_fpga0_peripheral_freqmhz=100 pcw_fpga1_peripheral_freqmhz=50 pcw_fpga2_peripheral_freqmhz=50 pcw_fpga3_peripheral_freqmhz=50
pcw_override_basic_clock=0 pcw_armpll_ctrl_fbdiv=26 pcw_iopll_ctrl_fbdiv=32 pcw_ddrpll_ctrl_fbdiv=21
pcw_cpu_cpu_pll_freqmhz=1300.000 pcw_io_io_pll_freqmhz=1600.000 pcw_ddr_ddr_pll_freqmhz=1050.000 pcw_use_m_axi_gp0=1
pcw_use_m_axi_gp1=0 pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0 pcw_use_s_axi_acp=0
pcw_use_s_axi_hp0=0 pcw_use_s_axi_hp1=0 pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0
pcw_m_axi_gp0_freqmhz=100 pcw_m_axi_gp1_freqmhz=10 pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10
pcw_s_axi_acp_freqmhz=10 pcw_s_axi_hp0_freqmhz=10 pcw_s_axi_hp1_freqmhz=10 pcw_s_axi_hp2_freqmhz=10
pcw_s_axi_hp3_freqmhz=10 pcw_use_cross_trigger=0 pcw_ftm_cti_in0=DISABLED pcw_ftm_cti_in1=DISABLED
pcw_ftm_cti_in2=DISABLED pcw_ftm_cti_in3=DISABLED pcw_ftm_cti_out0=DISABLED pcw_ftm_cti_out1=DISABLED
pcw_ftm_cti_out2=DISABLED pcw_ftm_cti_out3=DISABLED pcw_uart0_baud_rate=115200 pcw_uart1_baud_rate=115200
pcw_s_axi_hp0_data_width=64 pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp2_data_width=64 pcw_s_axi_hp3_data_width=64
pcw_irq_f2p_mode=DIRECT pcw_preset_bank0_voltage=LVCMOS 3.3V pcw_preset_bank1_voltage=LVCMOS 1.8V pcw_uiparam_ddr_enable=1
pcw_uiparam_ddr_adv_enable=0 pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_bus_width=32 Bit
pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_high_temp=Normal (0-85) pcw_uiparam_ddr_partno=MT41K128M16 JT-125 pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_device_capacity=2048 MBits pcw_uiparam_ddr_speed_bin=DDR3_1066F pcw_uiparam_ddr_train_write_level=1 pcw_uiparam_ddr_train_read_gate=1
pcw_uiparam_ddr_train_data_eye=1 pcw_uiparam_ddr_clock_stop_en=0 pcw_uiparam_ddr_use_internal_vref=0 pcw_ddr_port0_hpr_enable=0
pcw_ddr_port1_hpr_enable=0 pcw_ddr_port2_hpr_enable=0 pcw_ddr_port3_hpr_enable=0 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)
pcw_ddr_lpr_to_critical_priority_level=2 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_write_to_critical_priority_level=2 pcw_nand_peripheral_enable=0
pcw_nand_grp_d8_enable=0 pcw_nor_peripheral_enable=0 pcw_nor_grp_a25_enable=0 pcw_nor_grp_cs0_enable=0
pcw_nor_grp_sram_cs0_enable=0 pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs1_enable=0 pcw_nor_grp_sram_int_enable=0
pcw_qspi_peripheral_enable=1 pcw_qspi_qspi_io=MIO 1 .. 6 pcw_qspi_grp_single_ss_enable=1 pcw_qspi_grp_single_ss_io=MIO 1 .. 6
pcw_qspi_grp_ss1_enable=0 pcw_qspi_grp_io1_enable=0 pcw_qspi_grp_fbclk_enable=1 pcw_qspi_grp_fbclk_io=MIO 8
pcw_qspi_internal_highaddress=0xFCFFFFFF pcw_enet0_peripheral_enable=0 pcw_enet0_grp_mdio_enable=0 pcw_enet0_reset_enable=0
pcw_enet1_peripheral_enable=0 pcw_enet1_grp_mdio_enable=0 pcw_enet1_reset_enable=0 pcw_sd0_peripheral_enable=0
pcw_sd0_grp_cd_enable=0 pcw_sd0_grp_wp_enable=0 pcw_sd0_grp_pow_enable=0 pcw_sd1_peripheral_enable=0
pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_wp_enable=0 pcw_sd1_grp_pow_enable=0 pcw_uart0_peripheral_enable=0
pcw_uart0_grp_full_enable=0 pcw_uart1_peripheral_enable=1 pcw_uart1_uart1_io=MIO 48 .. 49 pcw_uart1_grp_full_enable=0
pcw_spi0_peripheral_enable=0 pcw_spi0_grp_ss0_enable=0 pcw_spi0_grp_ss1_enable=0 pcw_spi0_grp_ss2_enable=0
pcw_spi1_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0 pcw_spi1_grp_ss1_enable=0 pcw_spi1_grp_ss2_enable=0
pcw_can0_peripheral_enable=0 pcw_can0_grp_clk_enable=0 pcw_can1_peripheral_enable=0 pcw_can1_grp_clk_enable=0
pcw_trace_peripheral_enable=0 pcw_trace_grp_2bit_enable=0 pcw_trace_grp_4bit_enable=0 pcw_trace_grp_8bit_enable=0
pcw_trace_grp_16bit_enable=0 pcw_trace_grp_32bit_enable=0 pcw_wdt_peripheral_enable=0 pcw_ttc0_peripheral_enable=0
pcw_ttc1_peripheral_enable=0 pcw_pjtag_peripheral_enable=0 pcw_usb0_peripheral_enable=0 pcw_usb0_reset_enable=0
pcw_usb1_peripheral_enable=0 pcw_usb1_reset_enable=0 pcw_i2c0_peripheral_enable=0 pcw_i2c0_grp_int_enable=0
pcw_i2c0_reset_enable=0 pcw_i2c1_peripheral_enable=0 pcw_i2c1_grp_int_enable=0 pcw_i2c1_reset_enable=0
pcw_gpio_peripheral_enable=0 pcw_gpio_mio_gpio_enable=0 pcw_gpio_emio_gpio_enable=0 pcw_apu_clk_ratio_enable=6:2:1
pcw_enet0_peripheral_freqmhz=1000 Mbps pcw_enet1_peripheral_freqmhz=1000 Mbps pcw_cpu_peripheral_clksrc=ARM PLL pcw_ddr_peripheral_clksrc=DDR PLL
pcw_smc_peripheral_clksrc=IO PLL pcw_qspi_peripheral_clksrc=IO PLL pcw_sdio_peripheral_clksrc=IO PLL pcw_uart_peripheral_clksrc=IO PLL
pcw_spi_peripheral_clksrc=IO PLL pcw_can_peripheral_clksrc=IO PLL pcw_fclk0_peripheral_clksrc=IO PLL pcw_fclk1_peripheral_clksrc=IO PLL
pcw_fclk2_peripheral_clksrc=IO PLL pcw_fclk3_peripheral_clksrc=IO PLL pcw_enet0_peripheral_clksrc=IO PLL pcw_enet1_peripheral_clksrc=IO PLL
pcw_can0_peripheral_clksrc=External pcw_can1_peripheral_clksrc=External pcw_tpiu_peripheral_clksrc=External pcw_ttc0_clk0_peripheral_clksrc=CPU_1X
pcw_ttc0_clk1_peripheral_clksrc=CPU_1X pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc1_clk0_peripheral_clksrc=CPU_1X pcw_ttc1_clk1_peripheral_clksrc=CPU_1X
pcw_ttc1_clk2_peripheral_clksrc=CPU_1X pcw_wdt_peripheral_clksrc=CPU_1X pcw_dci_peripheral_clksrc=DDR PLL pcw_pcap_peripheral_clksrc=IO PLL
pcw_usb_reset_polarity=Active Low pcw_enet_reset_polarity=Active Low pcw_i2c_reset_polarity=Active Low pcw_fpga_fclk0_enable=1
pcw_fpga_fclk1_enable=0 pcw_fpga_fclk2_enable=0 pcw_fpga_fclk3_enable=0 pcw_nor_sram_cs0_t_tr=1
pcw_nor_sram_cs0_t_pc=1 pcw_nor_sram_cs0_t_wp=1 pcw_nor_sram_cs0_t_ceoe=1 pcw_nor_sram_cs0_t_wc=2
pcw_nor_sram_cs0_t_rc=2 pcw_nor_sram_cs0_we_time=0 pcw_nor_sram_cs1_t_tr=1 pcw_nor_sram_cs1_t_pc=1
pcw_nor_sram_cs1_t_wp=1 pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_wc=2 pcw_nor_sram_cs1_t_rc=2
pcw_nor_sram_cs1_we_time=0 pcw_nor_cs0_t_tr=1 pcw_nor_cs0_t_pc=1 pcw_nor_cs0_t_wp=1
pcw_nor_cs0_t_ceoe=1 pcw_nor_cs0_t_wc=2 pcw_nor_cs0_t_rc=2 pcw_nor_cs0_we_time=0
pcw_nor_cs1_t_tr=1 pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_wp=1 pcw_nor_cs1_t_ceoe=1
pcw_nor_cs1_t_wc=2 pcw_nor_cs1_t_rc=2 pcw_nor_cs1_we_time=0 pcw_nand_cycles_t_rr=1
pcw_nand_cycles_t_ar=1 pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_wp=1 pcw_nand_cycles_t_rea=1
pcw_nand_cycles_t_wc=2 pcw_nand_cycles_t_rc=2
processing_system7_v5_5_processing_system7/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=processing_system7 x_ipversion=5.5 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_en_emio_pjtag=0 c_en_emio_enet0=0 c_en_emio_enet1=0
c_en_emio_trace=0 c_include_trace_buffer=0 c_trace_buffer_fifo_size=128 use_trace_data_edge_detector=0
c_trace_pipeline_width=8 c_trace_buffer_clock_delay=12 c_emio_gpio_width=64 c_include_acp_trans_check=0
c_use_default_acp_user_val=0 c_s_axi_acp_aruser_val=31 c_s_axi_acp_awuser_val=31 c_m_axi_gp0_id_width=12
c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_enable_static_remap=0 c_s_axi_gp0_id_width=6
c_s_axi_gp1_id_width=6 c_s_axi_acp_id_width=3 c_s_axi_hp0_id_width=6 c_s_axi_hp0_data_width=64
c_s_axi_hp1_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp2_data_width=64
c_s_axi_hp3_id_width=6 c_s_axi_hp3_data_width=64 c_m_axi_gp0_thread_id_width=12 c_m_axi_gp1_thread_id_width=12
c_num_f2p_intr_inputs=1 c_irq_f2p_mode=DIRECT c_dq_width=32 c_dqs_width=4
c_dm_width=4 c_mio_primitive=54 c_trace_internal_width=2 c_use_axi_nonsecure=0
c_use_m_axi_gp0=1 c_use_m_axi_gp1=0 c_use_s_axi_gp0=0 c_use_s_axi_hp0=0
c_use_s_axi_hp1=0 c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 c_use_s_axi_acp=0
c_ps7_si_rev=PRODUCTION c_fclk_clk0_buf=true c_fclk_clk1_buf=false c_fclk_clk2_buf=false
c_fclk_clk3_buf=false c_package_name=clg400

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=zynq
die=xc7z010clg400-1 package=clg400 speedgrade=-1 version=2015.2
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=1.000000 pct_inputs_defined=0 user_junc_temp=44.2 (C)
ambient_temp=25.0 (C) user_effective_thetaja=11.5 airflow=250 (LFM) heatsink=none
user_thetasa=0.0 (C/W) board_selection=medium (10"x10") board_layers=8to11 (8 to 11 Layers) user_thetajb=9.3 (C/W)
user_board_temp=25.0 (C) junction_temp=44.2 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=1.666730 dynamic=1.535072
effective_thetaja=11.5 thetasa=0.0 (C/W) thetajb=9.3 (C/W) off-chip_power=0.000000
clocks=0.009493 logic=0.004217 signals=0.004826 bram=0.001398
i/o=0.000032 ps7=1.515106 devstatic=0.131659 vccint_voltage=1.000000
vccint_total_current=0.026881 vccint_dynamic_current=0.019860 vccint_static_current=0.007022 vccaux_voltage=1.800000
vccaux_total_current=0.011695 vccaux_dynamic_current=0.000000 vccaux_static_current=0.011695 vcco33_voltage=3.300000
vcco33_total_current=0.001000 vcco33_dynamic_current=0.000000 vcco33_static_current=0.001000 vcco25_voltage=2.500000
vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco18_voltage=1.800000
vcco18_total_current=0.001000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.001000 vcco15_voltage=1.500000
vcco15_total_current=0.001000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.001000 vcco135_voltage=1.350000
vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco12_voltage=1.200000
vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vccaux_io_voltage=1.800000
vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccbram_voltage=1.000000
vccbram_total_current=0.000660 vccbram_dynamic_current=0.000106 vccbram_static_current=0.000554 mgtavcc_voltage=1.000000
mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000
mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtvccaux_voltage=1.800000
mgtvccaux_total_current=0.000000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 vccpint_voltage=1.000000
vccpint_total_current=0.738288 vccpint_dynamic_current=0.708450 vccpint_static_current=0.029838 vccpaux_voltage=1.800000
vccpaux_total_current=0.060043 vccpaux_dynamic_current=0.049713 vccpaux_static_current=0.010330 vccpll_voltage=1.800000
vccpll_total_current=0.018291 vccpll_dynamic_current=0.015291 vccpll_static_current=0.003000 vcco_ddr_voltage=1.500000
vcco_ddr_total_current=0.457616 vcco_ddr_dynamic_current=0.455616 vcco_ddr_static_current=0.002000 vcco_mio0_voltage=1.800000
vcco_mio0_total_current=0.004208 vcco_mio0_dynamic_current=0.003208 vcco_mio0_static_current=0.001000 vcco_mio1_voltage=1.800000
vcco_mio1_total_current=0.001250 vcco_mio1_dynamic_current=0.000250 vcco_mio1_static_current=0.001000 vccadc_voltage=1.800000
vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 confidence_level_design_state=High
confidence_level_clock_activity=High confidence_level_io_activity=Low confidence_level_internal_activity=Medium confidence_level_device_models=High
confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=1924 slice_luts_fixed=0 slice_luts_available=17600 slice_luts_util_percentage=10.93
lut_as_logic_used=1800 lut_as_logic_fixed=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=10.23
lut_as_memory_used=124 lut_as_memory_fixed=0 lut_as_memory_available=6000 lut_as_memory_util_percentage=2.07
lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=124 lut_as_shift_register_fixed=0
slice_registers_used=1740 slice_registers_fixed=0 slice_registers_available=35200 slice_registers_util_percentage=4.94
register_as_flip_flop_used=1740 register_as_flip_flop_fixed=0 register_as_flip_flop_available=35200 register_as_flip_flop_util_percentage=4.94
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=35200 register_as_latch_util_percentage=0.00
f7_muxes_used=0 f7_muxes_fixed=0 f7_muxes_available=8800 f7_muxes_util_percentage=0.00
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=4400 f8_muxes_util_percentage=0.00
slice_used=666 slice_fixed=0 slice_available=4400 slice_util_percentage=15.14
slicel_used=412 slicel_fixed=0 slicem_used=254 slicem_fixed=0
lut_as_logic_used=1800 lut_as_logic_fixed=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=10.23
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=1277 using_o6_output_only_fixed=
using_o5_and_o6_used=523 using_o5_and_o6_fixed= lut_as_memory_used=124 lut_as_memory_fixed=0
lut_as_memory_available=6000 lut_as_memory_util_percentage=2.07 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=124 lut_as_shift_register_fixed=0 using_o5_output_only_used=0 using_o5_output_only_fixed=
using_o6_output_only_used=112 using_o6_output_only_fixed= using_o5_and_o6_used=12 using_o5_and_o6_fixed=
lut_flip_flop_pairs_used=2190 lut_flip_flop_pairs_fixed=0 lut_flip_flop_pairs_available=17600 lut_flip_flop_pairs_util_percentage=12.44
fully_used_lut_ff_pairs_used=1129 fully_used_lut_ff_pairs_fixed= lut_ff_pairs_with_unused_lut_used=266 lut_ff_pairs_with_unused_lut_fixed=
lut_ff_pairs_with_unused_flip_flop_used=795 lut_ff_pairs_with_unused_flip_flop_fixed= unique_control_sets_used=99 minimum_number_of_registers_lost_to_control_set_restriction_used=252(Lost)
memory
block_ram_tile_used=2 block_ram_tile_fixed=0 block_ram_tile_available=60 block_ram_tile_util_percentage=3.33
ramb36_fifo_used=2 ramb36_fifo_fixed=0 ramb36_fifo_available=60 ramb36_fifo_util_percentage=3.33
ramb36e1_only_used=2 ramb18_used=0 ramb18_fixed=0 ramb18_available=120
ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=80 dsps_util_percentage=0.00
clocking
bufgctrl_used=1 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=3.13
bufio_used=0 bufio_fixed=0 bufio_available=8 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_fixed=0 mmcme2_adv_available=2 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=2 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=4 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=48 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=8 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=1593 fdre_functional_category=Flop & Latch lut6_used=722 lut6_functional_category=LUT
lut3_used=562 lut3_functional_category=LUT lut2_used=383 lut2_functional_category=LUT
lut5_used=338 lut5_functional_category=LUT lut4_used=299 lut4_functional_category=LUT
fdse_used=147 fdse_functional_category=Flop & Latch bibuf_used=130 bibuf_functional_category=IO
srlc32e_used=105 srlc32e_functional_category=Distributed Memory carry4_used=42 carry4_functional_category=CarryLogic
srl16e_used=31 srl16e_functional_category=Distributed Memory lut1_used=19 lut1_functional_category=LUT
ibuf_used=8 ibuf_functional_category=IO obuf_used=4 obuf_functional_category=IO
ramb36e1_used=2 ramb36e1_functional_category=Block Memory ps7_used=1 ps7_functional_category=Specialized Resource
bufg_used=1 bufg_functional_category=Clock
io_standard
pci33_3=0 lvcmos15=0 lvttl=0 diff_sstl18_ii=0
hstl_i=0 mobile_ddr=0 lvcmos12=0 lvcmos33=1
diff_sstl15=1 hstl_ii=0 diff_mobile_ddr=0 hsul_12=0
lvcmos25=0 lvcmos18=1 hstl_i_18=0 diff_hsul_12=0
hstl_ii_18=0 sstl18_i=0 sstl18_ii=0 sstl15=1
sstl15_r=0 sstl135=0 sstl135_r=0 lvds_25=0
diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0
diff_sstl18_i=0 diff_sstl15_r=0 diff_sstl135=0 diff_sstl135_r=0
blvds_25=0

router
usage
lut=2206 ff=1740 bram36=2 bram18=0
ctrls=99 dsp=0 iob=12 bufg=0
global_clocks=1 pll=0 bufr=0 nets=8158
movable_instances=4570 pins=26986 bogomips=0 high_fanout_nets=2
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=2432292 actual_expansions=1385999 router_runtime=16.768000

synthesis
command_line_options
-part=xc7z010clg400-1 -name=default::[not_specified] -top=system_wrapper -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=default::10000
-shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:02:20s memory_peak=885.359MB memory_gain=612.352MB hls_ip=0