------------------------------------------------------------
-- mult_plus.vhd
--
-- This file supports the demonstration of a Xilinx
-- based Multiply Unit in the absence of external
-- clock and external controller.
-- The clock is provided by a clockdiv module which
-- divides the 12 MHz on board clock down to a more sedate
-- 12 Hz while the controller is provided as a separate
-- VHDL module.
--
-- For synthesis of this file you will also need 
-- to synthesize the files:
--   mult.vhd        which contains the components of the VMU
--   controller.vhd  which contains a model for a simple controller
--
-- For operation the circuit must be connected to the SPARC
-- board via the dedicated cable and to a normally high
-- nRESET input.
--
------------------------------------------------------------

------------------------------------------------------------
-- Entity and architecture for clock division circuit
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clockdiv is
  port (fastclock, nreset : in std_logic;
        slowclock : out std_logic
        );
end entity clockdiv;

architecture behaviour of clockdiv is

  signal count : unsigned(19 downto 0);

begin

  process(fastclock, nReset) is
    begin
      if (nReset = '0' ) then
        count <= (others => '0');
      elsif rising_edge(fastclock) then
        count <= count + 1;
      end if;
    end process;

    slowclock <= std_logic( count(19) ) ;
    -- slowclock <= fastclock ;

end architecture behaviour;

------------------------------------------------------------
-- Entity and architecture for complete multiplier plus controller
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity vmu_plus is
  port (clock12MHz, nReset, H2, C3, C2 : in std_logic;
        portB : inout std_logic_vector(7 downto 0);
        H3, H1 : inout std_logic; -- not INOUT but readable OUT
        Start, LsbB, EmptyB, FullB : inout std_logic; -- not INOUT but readable OUT
	segA, segB, segC, segD, segE, segF, segG,
	ucRESET, ramDISABLE: out std_logic);
end entity vmu_plus;

architecture structure of vmu_plus is

  component vmu is
  port (clock12MHz : in std_logic;
        clock : in std_logic;
        nReset, H2, C3, C2 : in std_logic;
        portB : inout std_logic_vector(7 downto 0);
        H3, H1 : inout std_logic; -- not INOUT but readable OUT
        Start, LsbB, EmptyB, FullB : inout std_logic; -- not INOUT but readable OUT
        UpdateA, UpdateB, UpdateP, Shift, ZeroP, Subtract, EnableP : in std_logic;
	segA, segB, segC, segD, segE, segF, segG,
	ucRESET, ramDISABLE: out std_logic);
  end component vmu;

  component controller is
  port (clock, nReset : in std_logic;
        Start : in std_logic;
        LsbB, EmptyB, FullB : in std_logic;
        UpdateA, UpdateB, UpdateP, Shift, ZeroP, Subtract, EnableP: out std_logic
        );
  end component controller;

  component clockdiv is
  port (fastclock, nreset : in std_logic;
        slowclock : out std_logic
        );
  end component clockdiv;

  signal clock : std_logic;
  signal UpdateA, UpdateB, UpdateP, Shift, ZeroP, Subtract, EnableP : std_logic;

begin
  vmu_inst : vmu
  port map (clock12MHz,
        clock,
        nReset, H2, C3, C2,
        portB,
        H3, H1,
        Start, LsbB, EmptyB, FullB,
        UpdateA, UpdateB, UpdateP, Shift, ZeroP, Subtract, EnableP,
	segA, segB, segC, segD, segE, segF, segG,
	ucRESET, ramDISABLE
        );

  controller_inst : controller
  port map (clock, nReset,
        Start,
        LsbB, EmptyB, FullB,
        UpdateA, UpdateB, UpdateP, Shift, ZeroP, Subtract, EnableP
        );

  clockdiv_inst : clockdiv
  port map (clock12MHz, nReset, clock);

end architecture structure;