CMOS Gate Array Design Exercise 1999

Design Specification

Frame Synchronization Unit

Introduction

This year's exercise is to design a frame synchronization unit for use in mobile communications. The unit should lock on to incoming frames which use a frame alignment word.

Frames & Frame Alignment Words

For digital transmission, data may be divided into frames, with error detection and correction being on a frame by frame basis. Where errors are not correctable, the receiver may request that the frame be resent. In a mobile environment with multiple paths from the transmitter to the receiver, one of the major problems is maintaining frame synchronization.

Frames may be identified by a frame alignment word which is sent at the beginning of each frame. The following picture illustrates two 8 bit data frames each of which has a 3 bit frame alignment word. The constant frame alignment word is 001₂.

note that both the frame alignment word, 001₂, and the data are transmitted least significant bit first.

If the transmitter and receiver are synchronized, the receiver will know when to expect the next frame alignment word. If the frame alignment word is not present as expected, then the receiver knows that synchronization is lost.

Where synchronization between the transmitter and receiver is lost, the the receiver waits for a new frame alignment word. Synchronization is regained if two such alignment words are detected with appropriate separation.

Frame Synchronization Unit

The frame synchronization unit that you will design, monitors the incoming DATA signal and produces a STROBE output coincident with the first bit of frame data (d0 in the above diagram) when the unit has locked onto (i.e. synchronized with) the DATA signal. In addition a SYNC output indicates that synchronization has been achieved. This output remains high until synchronization is lost.

The following figures illustrate this operation:

Synchronization is gained
(two correctly spaced frame alignment words are detected)

Normal synchronized operation

Synchronization is lost
(an error in the frame alignment word is detected)

These simple examples have used a 3 bit frame alignment word within an 8 bit frame. For this exercise you should aim for a 6 bit frame alignment word within a 32 bit frame.

Detailed Specification

Your design for the frame synchronization unit must satisfy the following specification:

• You can only use the gates which are available on the ULA:
  • AND_2 OR_2 XOR_2 XNOR_2 INV NAND_4 NAND_3 NAND_2 NOR_3 NOR_2
  • D_TYPE macro

• Synchronous Design:

  All designs must be fully synchronous. Major penalties will be incurred by teams who adopt asynchronous or quasi-synchronous design styles; as well as losing marks you will probably find that your design doesn't work.

  A fully synchronous design contains no spurious state elements; no RS flip-flops, no transparent latches and no feedback paths within combinational logic blocks. The only state elements will be the the edge triggered D-types as supplied in the ULA library.

• The design must support the following inputs and ouptuts:

  Inputs

  • CLOCK

    A single clock signal with an active rising edge is common to all D-types. You should not attempt to connect this signal to any gate input or output which is not labelled CLOCK.

  • nRESET

    A single active-low asynchronous reset signal is common to all D-types, this input is used for initialization only. You should not attempt to connect this signal to any gate input or output which is not labelled nRESET.

  • DATA

    Serial data input. Since this input comes from a potentially noisy data channel it is suggested that you re-time it using a single D-type before using it in other parts of the circuit.

  • FAW5...FAW0

    These six inputs are used to define the expected frame alignment word.

  Outputs

  • STROBE

    The STROBE output must go high for 1 clock cycle coincident with the first bit of frame data when the receiver is synchronized. It is low at all other times.

  • SYNC

    The SYNC output goes high when synchronization is achieved (coincident with STROBE going high). It will remain high until synchronization is lost.

Suggested Division into Modules

To help in the development and testing of this year's designs it has been decided to make a suggestion on the initial splitting of your circuit into separately testable blocks. All submitted designs should exhibit more testability than described here (more circuit breaks to improve observability and controllability and more test outputs to improve observability only).

The suggested split is into three blocks. With the exception of common CLOCK and nRESET inputs, the blocks are independent.

• Compare Module

  This module produces a MATCH ouput each time the frame alignment word is detected.

• Counter Module

  This module counts the interval between detected matches and produces an EXPECTED signal indicating that another MATCH is expected. Matches which occur before they are expected are assumed to be spurious and ignored.

• Decsision Module

  This module sets the STOBE and SYNC outputs based on the MATCH and EXPECTED signals from the other modules.

During the testing stage, the separate blocks will be reconnected to give the originally specified functionality. Due to the careful choice of signal names, this split circuit will simulate as if it was reconnected thereby assisting with design verification.

Flexibilty in Specification

To cope with teams of differing capabitilies, there are a number of ways in which the specification may be relaxed:

• Frame Size

  The standard frame size for this exercise is 32 bits (including the frame alignment word). To simplify your design you may like to reduce the number of bits in the frame. Acceptable frame sizes will be between 15 and 32 bits.

  You must redefine the, framesize, simulation variable in order to simulate a design with reduced frame size. e.g. setting simulation option +define+framesize=16 will set the frame size to 16.

  The simulation option may be added to the additional parameters field in the Icebox's Remote CAD Tools dialogue box or can be set directly on the verilog_xl command line.

• Frame Alignment Word Length

  The standard frame alignment word length for this exercise is 6 bits. This may also be reduced in order to simplify your design. Acceptable frame alignment word lengths will be between 4 and 6 bits. Note that if you use only 5 (or 4) bits you should not include inputs FAW5 (or FAW5 & FAW4) in your design.

  The simulation option +define+fawlength=4 will set the frame alignment word length to 4 for simulation.

• Fixed Frame Alignment Word

  Another possibility is to use a fixed frame alignment word rather than a programmable one. In this case the FAW5..FAW0 inputs should be omitted from your design. Again the frame alignment word size should be between 4 and 6 bits. Note that when selecting a fixed word, there must be at least one bit change along its length. Thus 000000₂ and 1111₂ are unacceptable while 00001₂ and 101000₂ would be OK.

  The simulation option +define+faw=1 will set the frame alignment word to 1₁₀ for simulation.

Making an informed choice

The choice of a circuit for implementation will be one of your most important design decisions for this exercise. In the initial stages you may like to produce outline designs for a number of different options. It is certainly possible that one or more of your initial designs will need more than the 67 available gate sites.

In choosing between designs, the key points to consider are:

1. Although an elegant design which fully meets the spec will get most marks, a simple functional design will get more marks than an ambitious design that doesn't quite work or is not completed on time.
2. As you use more of the ULA the wiring becomes harder. Thus a design which uses all 67 available gate sites may take twice as long to route as one that uses only 57.

Note that if you chose to relax the specification such as described above you must document this in both your interim and your final reports.