------------------------------------------------------------
-- Entity and architecture for 32 bit frame buffer
--
-- The frame buffer is a constantly shifting shift register
-- which stores the last 32 bits from the data input
-- The outputs will be valid (i.e. the Frame alignment
-- word will align with "faw" output) for only one cycle
-- in 32. This cycle should be indicated by the STROBE
-- output from the Frame Sychronization Unit.
-- During this cycle data may be processed.
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity frame_buffer is
  port (clock, nReset, data: in std_logic;
        faw : out std_logic_vector(5 downto 0);
        frame_data : out std_logic_vector(6 downto 0);
        station_address : out std_logic_vector(4 downto 0);
        frame_number : out std_logic_vector(3 downto 0);
        parity : out std_logic_vector(8 downto 0));
end entity frame_buffer;

architecture behaviour of frame_buffer is

  signal sreg : std_logic_vector(31 downto 0);

begin

  faw <= sreg(31 downto 26);
  frame_data <= sreg(6 downto 0);
  station_address <= sreg(11 downto 7);
  frame_number <= sreg(15 downto 12);
  parity <= sreg(24 downto 16);

  shift: process(clock, nReset) is
    begin
      if (nReset = '0' ) then
        sreg <= "00000000000000000000000000000000";
      elsif rising_edge(clock) then
        sreg(31) <= data;
        sreg(30 downto 0) <= sreg(31 downto 1);
      end if;
    end process shift;

end architecture behaviour;


------------------------------------------------------------
-- Entity and architecture for output buffer unit
--
-- The output buffer converts the parallel frame data
-- into a serial data stream suitable for conversion
-- to RS232 levels by an RS232 tranceiver
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity output_buffer is
  port (clock, nReset, strobe, enable: in std_logic;
        frame_data : in std_logic_vector(6 downto 0);
        serial_out: out std_logic);
end entity output_buffer;

architecture behaviour of output_buffer is

  signal sreg : std_logic_vector(7 downto 0);

begin

  serial_out <= sreg(0);

  shift: process(clock, nReset) is
    begin
      if (nReset = '0' ) then
	-- On reset fill the shift register with idle bits.
	-- '1' is the idle state for the RS232
        sreg <= "11111111";
      elsif rising_edge(clock) then
        if (strobe = '1') and (enable = '1') then
	  -- Copy the data to the shift register ready for output
	  -- The '0' here is the single start bit which will be
	  -- output before the frame data.
          sreg(7 downto 1) <= frame_data;
          sreg(0) <= '0';
        else
	  -- The default action is to shift data out of the
	  -- shift register and to shift in further '1's
          -- The '1' provides the stop bits and further idle bits
	  -- which will be output after the frame data.
          sreg(7) <= '1';
          sreg(6 downto 0) <= sreg(7 downto 1);
        end if;
      end if;
    end process shift;

end architecture behaviour;


------------------------------------------------------------
-- Entity and architecture for complete decoder
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity decode is
  port (CLOCK, nRESET, DATA, STROBE: in std_logic;
        SERIAL_OUT,
	segA, segB, segC, segD, segE, segF, segG,
	ucRESET, ramDISABLE: out std_logic);
end entity decode;

architecture structure of decode is

  component frame_buffer is
    port (clock, nReset, data: in std_logic;
        faw : out std_logic_vector(5 downto 0);
        frame_data : out std_logic_vector(6 downto 0);
        station_address : out std_logic_vector(4 downto 0);
        frame_number : out std_logic_vector(3 downto 0);
        parity : out std_logic_vector(8 downto 0));
  end component frame_buffer;

  component output_buffer is
    port (clock, nReset, strobe, enable: in std_logic;
        frame_data : in std_logic_vector(6 downto 0);
        serial_out: out std_logic);
  end component output_buffer;

  signal faw : std_logic_vector(5 downto 0);
  signal frame_data : std_logic_vector(6 downto 0);
  signal station_address : std_logic_vector(4 downto 0);
  signal frame_number : std_logic_vector(3 downto 0);
  signal parity : std_logic_vector(8 downto 0);
  signal enable : std_logic;

begin
  --Display the number "1" on the 7 segment display
  --This simple fixed status message informs us that the
  --"decode.bit" image has been downloaded.
  --A more advanced system will provide more status information
  --to the user via this 7 segment display.
      segA <= '0';
  segF <= '0';  segB <= '1';
      segG <= '0';
  segE <= '0';  segC <= '1';
      segD <= '0';

  ramDISABLE <= '1'; -- Disable the RAM on the Xilinx board
  ucRESET <= '1'; -- Reset and hence disable the microcontroller

  --Setting enable <= '1' results in data from the frame buffer being
  --copied to the output buffer.
  --A more advanced system will only copy data to the output buffer if
  --it is addressed to this station.
  --It may also be appropriate to reject data with uncorrectable errors.
  enable <= '1';

  fb_inst : frame_buffer
    port map (CLOCK, nRESET, DATA, faw, frame_data, station_address, frame_number, parity);

  ob_inst : output_buffer
    port map (CLOCK, nRESET, STROBE, enable, frame_data, SERIAL_OUT);

end architecture structure;