Using Simulation as part of a Modular Design Strategy

The simple simulation system supported by the Remote CAD Tools dialogue is a turnkey system which will run a pre-defined simulation on a completed design, giving a waveform display and a simple pass/fail result.

Having received a fail result, it can be difficult to identify the cause (given a complex circuit made up of a number of connected modules).

In order to make best use of simulation as a design tool you will want to run customized simulations of modules. Using this technique you can design a module or sub-circuit and then test it before going on to the next module. Thus each module is known to be correct before it is connected to the full circuit, making design debugging much easier.

• Customizing Your Simulation

  After having netlisted your design you can run a simulation manually rather than using the turnkey system. This will give you the oportunity to customize the simulation.

  1. Ensure that the exceed program is running on your workstation.

  2. Telnet to salvador.

  3. Make a new directory and change to that directory:
     e.g.
     mkdir design_2/custom_sim
     cd design_2/custom_sim

  4. Create the simulation files:
     either
     simulate_final schematic design
     or
     simulate_final layout design
     assuming that your cellname is design.

  5. You can now run the simulation:
     verilog_xl design_stim.v design.v dtype.v

  6. The simulation can be customized by editing the file design_stim.v.
     In particular you may like to change the stimulus (input) waveforms and/or view internal nodes within your circuit. In order to help you with this task, the stimulus and waveform display sections are identified by comments in the design_stim.v file. Details on these and other customizations can be found in the on-line Verilog-XL documentation.

• Simulation of modules

  In order to simulate a module or sub-circuit rather than the full design, the simulate_any command is used in place of simulate_final during a customized simulation. By editing the stimulus information you should be able to simulate simple state machines or combinational logic blocks without recourse to a full system test.

  notes:

  • Currently this system will only work for schematics and is primarily for use on full modules. Where a module is split for testability, this simulation will not re-connect the broken links making the simulation harder to control and interpret.
  • Although an uncustomized simulation is possible it will be of little use since the default stimulus is very simple.