# PAD RING DEFINITION FILE	

# FORMAT:
#
#	CORE		<core_module_name>
#
# if no CORE line exists, the default core module name is topcell
#
#	WRAPPER		<wrapper_module_name>
#
# if no WRAPPER line exists, the default wrapper module name is wrap_<core_module_name>
#
#	INSTANCE	<core_instance_name>
#
# if no INSTANCE line exists, the default core instance name is core_instance
#
#	<side>,	<pad_type>,	<external_port_name>,	<internal_port_name(s)_if_different>
#
# where <side> is one of:
#	TOP
#	BOTTOM
#	LEFT
#	RIGHT
#
# and <pad_type> is one of:
#	INPUT
#	OUTPUT
#	OUTPUT_TRISTATE
#	INPUT_PULLUP
#	INOUT
#	PADS_VDD
#	PADS_GND
#	CORE_VDD
#	CORE_GND

# DEFAULT PORT ORDER IS ANTICLOCKWISE

WRAPPER		cpu
CORE		cpu_core
INSTANCE	CPU_core

BOTTOM	INPUT_PULLUP	nIRQ	
BOTTOM	INOUT		Data[0]		ENB	Data_in[0]	Data_out[0]
BOTTOM	INOUT		Data[1]		ENB	Data_in[1]	Data_out[1]
BOTTOM	INOUT		Data[2]		ENB	Data_in[2]	Data_out[2]
BOTTOM	PADS_VDD
BOTTOM	INOUT		Data[3]		ENB	Data_in[3]	Data_out[3]
BOTTOM	INOUT		Data[4]		ENB	Data_in[4]	Data_out[4]
BOTTOM	INOUT		Data[5]		ENB	Data_in[5]	Data_out[5]

RIGHT	INOUT		Data[6]		ENB	Data_in[6]	Data_out[6]
RIGHT	INOUT		Data[7]		ENB	Data_in[7]	Data_out[7]
RIGHT	INOUT		Data[8]		ENB	Data_in[8]	Data_out[8]
RIGHT	PADS_GND
RIGHT	CORE_GND
RIGHT	INOUT		Data[9]		ENB	Data_in[9]	Data_out[9]
RIGHT	INOUT		Data[10]	ENB	Data_in[10]	Data_out[10]
RIGHT	INOUT		Data[11]	ENB	Data_in[11]	Data_out[11]

TOP	INOUT		Data[12]	ENB	Data_in[12]	Data_out[12]
TOP	INOUT		Data[13]	ENB	Data_in[13]	Data_out[13]
TOP	INOUT		Data[14]	ENB	Data_in[14]	Data_out[14]
TOP	PADS_GND
TOP	INOUT		Data[15]	ENB	Data_in[15]	Data_out[15]
TOP	OUTPUT		ALE	
TOP	OUTPUT		nME	
TOP	INPUT_PULLUP	nWait	

LEFT	OUTPUT		nOE	
LEFT	OUTPUT		RnW	
LEFT	OUTPUT		SDO	
LEFT	CORE_VDD
LEFT	INPUT		SDI	
LEFT	INPUT		Test	
LEFT	INPUT_CLOCK	Clock	
LEFT	INPUT		nReset