Integrated Circuit Engineering 2

Lab 2 S-Edit

Introduction

This lab is provided as an introduction to the use of S-Edit. S-Edit can help with circuit design (in conjunction with T-Spice) and with layout verification (in conjunction with LVS). Both of these uses will be covered in this laboratory.

Example Library Files

The S-Edit library file, W:\TannerLibs\sedit_lab\schematic.sdb, contains symbols and schematics for the leaf cells and modules encountered in the first laboratory (EX_INV, EX_NAND2, EX_NOR2, EX_RING, EX_NAND2_LD & EX_NOR2_LD) in addition it contains the symbol and schematic for an OR-AND-INVERT compound gate, EX_OAI22.

The symbol and schematic for this compound gate, EX_OAI22, are shown in simplified form below:

The L-Edit library file, W:\TannerLibs\sedit_lab\layout.tdb, contains layouts for the initial cells encountered in the first laboratory (EX_INV, EX_NAND2 & EX_RING) and a partial layout for the compound gate, EX_OAI22.

The stick diagram and abstract for the partial layout are shown below:

Note that the pull down network (consisting of the NMOS transistors) has been wired whereas only the line of diffusion for the pull up network has been placed.

Note also that this gate uses a different approach to substrate connections; the EX_INV and EX_NAND2 gates used a combined contact and tap at one end of a line of diffusion, whereas the EX_OAI22 gate uses a line of taps along the each power rail. The first approach leads to wider cells while the second produces taller cells. For this reason it is not usual to mix the styles within a cell library where all cells should be the same height.

Procedure

Copy and Examine Schematic Library

Take a copy of the example schematic file W:\TannerLibs\sedit_lab\schematic.sdb and save it in your own user space. Open the new schematic.sdb file using S-Edit.

EX_OAI22 schematic and symbol
Initially you should see the schematic for the EX_OAI22 cell. You can swap to see the symbol by selecting View->Symbol Mode and swap back to the schematic by selecting View->Schematic Mode.
The schematic is constructed from a number of module instances and ports connected together with wires.
The symbol view is constructed from a number of lines, polygons, circles, boxes and text comments which make up the symbol that we see instanced in other schematics. In addition the symbol view includes ports which are not visible when the symbol is instanced. The ports on the schematic view of any module should match those on the symbol view.
Lines, polygons, circles, boxes and text comments may be included on a schematic but do not affect the function of the circuit. Beware joining instances with lines instead of wires, your circuit may look fine but the lines will be ignored leaving floating nodes.
Although text comments on the schematic are ignored there are other text annotations which affect the schematic. These are node names and instance parameters:
- Node Names
  The nodeX1, nodeX2 and nodeX3 annotations on the schematic are node names attached to the wiring. In this case the node names have been added to make debugging the Spice netlist easier (where node names are not explicitly given, node numbers will be allocated at the whim of the extraction tool during netlist creation).
  Node names are also used on schematics to "join by name" where two wires are considered connected since they share the same node name without cluttering the diagram with excess wiring.
- Instance Parameters
  By default all NMOS and PMOS transistors are set up with a gate length, L, of 600nm and gate width, W, of 1.5µm. These values are parameters of the transistors and are shown to the right of each instance. They can be modified from their default values by selecting the transistor instance on the schematic (it should change colour to indicate that it is selected) and then invoking the edit object function (Edit->Edit Object...).
EX_RING schematic and other modules
Open the EX_RING module (Module->Open...). You should see a schematic for the EX_RING design encountered in the first lab session. You may like to browse through the other modules for example to look at the symbols and schematics for the components of EX_RING (EX_NAND2 & EX_INV). Some top-level modules have only schematic views (e.g. EX_RING & EX_NAND2_LD) while true leaf modules have only symbol views (NMOS, PMOS, GND & VDD). If you find yourself looking at a blank screen you may need to swap views using View->Schematic Mode or View->Symbol Mode.

Simulate the EX_OAI22 Schematic

Extract
Open the EX_OAI22 schematic and initiate the extraction process (File->Export...). The default options in the export dialogue should be fine. They include selection of a suitable name for the output file name (EX_OAI22.sp) and selection of the correct export data type (SPICE File).
Set up Simulation
Start up T-Spice and open the EX_OAI22.sp file that you have created. Then add commands to the bottom of the file (but before the .END statement).
MOS models
For simulation of MOS transistors you must add a command forcing T-Spice to include AMI 0.5 µm NMOS and PMOS models from the mAMIs05.md file:
.include W:\TannerLibs\mAMIs\mAMIs05.md
All of the remaining commands may be typed by hand or added via the T-Spice Command Tool (Edit->Insert Command...).
Power Supply
Add a 5V DC voltage source between nodes VDD and GND:
Vvdd VDD GND 5
Input Stimulus
Add the following bit pattern voltage stimulus for the input nodes, A-D:
```
Va A GND BIT({0110})
Vb B GND BIT({00111100})
Vc C GND BIT({0000111111110000})
Vd D GND BIT({0000000011111111})
```
Note the A and B stimulus inputs repeat as many times as necessary and that all sixteen possible input combinations are included following a Gray code sequence in which only one input changes at any one time. The following figure shows the pattern of the input stimulus and the expected result for the OR AND INVERT gate:

Analysis
Select a transient analysis of duration 160ns with a step size of 10ps.
.tran 10p 160n
Output
View the transient voltages on the input and output nodes
.print tran v(Y) v(D) v(C) v(B) v(A)
Simulate and View Results
Run the simulation (Simulation->Run Simulation...) and select option for the display of waveforms during the simulation. Check that the result is as expected.

Copy and Examine Layout Library

Take a copy of the example layout file W:\TannerLibs\sedit_lab\layout.tdb and save it in your own user space in the same directory as the schematic.sdb file. Open the new layout.tdb file using L-Edit. Confirm that the layout of the EX_OAI22 cell matches the incomplete stick diagram shown above.

Complete the EX_OAI22 Layout

Complete the wiring of the PMOS transistors in the pull up network according to the stick diagram below:

There is a mistake in this stick diagram. We will ignore the problem now and attempt to solve it later.

Simulate the EX_OAI22 Layout

Extract and simulate the layout in the manner used in the first lab session. The input stimulus should be the same as that used to simulate the schematic. Note that, for layout simulation, there is no need to explicitly add the MOS models to the Spice file since they should be added automatically during extraction.

Confirm that the result is functionally the same as for the schematic simulation. Timing will differ since only the layout simulation takes account of delays due to parasitic capacitances. If the result is not the same, re-check your wiring.

Perform LVS check

A layout versus schematic (LVS) check is an important part of any full custom design flow. We check that layouts produced by hand match the schematics from which they were developed.

Start LVS and Open a new LVS Setup
LVS is found in the Tanner EDA program group. Start the program and open a new LVS Setup using the File->New command. Give the setup the name EX_OAI22.vdb using the File->Save As command.
Select netlists for comparison
Use the browse buttons to find the two SPICE netlists that you have created. The layout netlist will be have a ".spc" extension (EX_OAI22.spc) while the schematic netlist will be have a ".sp" extension (EX_OAI22.sp).
Set LVS Options
On the Parasitics card select the Remove Capacitors option setting the threshold for removal at a very large value so that all capacitors are ignored. For capacitors 1 (Farrad) is a suitably large value.
On the Output card select all the tick boxes in the Display Options:Screen section to provide maximum information in the event of failure.
Run LVS Check and Examine the Results
To run the check use the Verification->Run command.
You should be informed of problems with the a mismatch in the number of nodes in each netlist. This indicates that the check will fail. Opt to continue anyway so that you can check the results.
Examine the "Report of Nodes" produced by the LVS run. Fragmented classes are indicated where there is no match between the nodes in the schematic and those in the layout. Since all schematic nodes are named it is trivial to establish which node has been incorrectly wired in the layout. Where this is not so you may have to consult the two Spice netlists to trace a fault based on the node names provided during extraction and included in the LVS output.
Other mismatches may be flagged in different ways. Where it is not obvious what is causing the mismatch, consult the LVS on-line documentation: Help->LVS Users Guide. The section on Netlist Comparison Basics (pp498-) would be a good place to start.
Correct the Layout
Identify the fault in the stick diagram and correct both the stick diagram and the layout. Extract a new netlist and run a new LVS comparison to check the final layout.

Note that LVS has picked up a fault not spotted by apparently exhaustive test vectors applied during simulation. The reason is that a node allowed to float during the simulation will retain its voltage due to capacitance effects. The result will be different if the same test vectors are applied in a different order.

Further Use of S-Edit

If you have time

To further familiarize yourself with S-Edit you might like to:

Run a simulation of the EX_RING schematic provided in the schematic.sdb library. Note that the delays observed are shorter than for the layout simulation since parasitic capacitances are ignored.
Run an LVS to compare the EX_NAND2_LD cell you produced in the first lab with that included in schematic.sdb. Also compare schematic and layout for EX_NOR2_LD.

Use of S-Edit for Assignment

Circuit Design
From this brief introduction to S-Edit you should see that we can simulate circuits before layout, allowing development of your complete design in a bottom-up fashion (leaf cells first).
If you wish to perform some top-down development, simulating the gate level design before the implementation of gates is considered, a special library containing zero delay dummy gates has been created:
```
  W:\TannerLibs\generic\GATELib.sdb
```
The simulation procedure is the same as used above except that no MOS models or power supply need be added to the Spice netlist. For best results set the transient analysis timestep to 100ps. Note that a mixed simulation using some real gates and some zero delay gates may be possible but is as yet untested and may cause Spice to fail.
Circuit Optimization
If for instance you wish to check transistor sizing it is usual to do this on the schematic. It is much easier to modify transitor sizes and check simulation results on the schematic rather than on the layout. Although absolute delays will be greater when parasitics are considered, relative values such as the ratio of rise and fall times on an output are unlikely to change significantly.
Layout Verification
Using LVS to check your design as you go along (first leaf cells then modules and finally the top cell) is a faster and often more reliable check of your layout than simulation. The layout of your design will be a big task; proper layout verification will save you lots of time.
Documentation
Well drawn schematics are an essential part of your final report. If you draw them well during development, no additional effort is required to produce them for the report.

S-Edit Limitations

S-Edit is the least developed of the tools in the Tanner toolset (possibly because Tanner expect commercial customers to purchase a third party schematic package). There are a couple of limitations that you should be aware of:

No colour difference between lines and wires
Since all schematics are in black and white, wires and lines are indistinguishable. Remember to use wires for joining components on a schematic.
No automatic generation of default symbols from schematics
Many schematic tools will generate default symbols from schematics. The user need only modify the default if fancy features are required. In S-Edit, symbol generation is by hand. To save you time when creating symbols it is useful to copy a symbol from an existing module. S-Edit provides a library of symbols (with no schematics attached) intended for this purpose:
```
  V:\Tanner\S-Edit\library\element.sdb
```