Integrated Circuit Engineering 2

Advice on LVS options

The following options are those most useful for comparing transistor netlists generated from L-Edit and S-Edit:

• Input Card:
  • Netlists : Layout Netlist

    This is the T-Spice netlist extracted from L-Edit. Although voltage sources for stimulus and other simulation related information may be present in this file, they are not necessary and will be ignored during netlist comparison. The layout netlist will normally have a file name of the form:

    cellname.spc

  • Netlists : Schematic Netlist

    This is the T-Spice netlist exported from S-Edit. As with the layout netlist, simulation information will be ignored. The schematic netlist will normally have a file name of the form:

    cellname.sp

  • Optional Input Files : Prematch File

    This optional file allows for a more exacting LVS check by telling the system which named nodes on the schematic should be matched by named nodes on the layout. The norm in this case is a list of ports for the module to be checked. For a nand3 gate with ports: A,B,C & Y, we might have a file of the form:

      		A	A
      		B	B
      		C	C
      		Y	Y
    

    Sometimes the node names may not be the same. For a d-type flip-flop we might have a file of the form:

      		D	D
      		Q	Q
      		nQ	Qbar
      		CLK	Clock
      		nRST	RESETbar
    

    where the names on the left are the names used in the layout view while those on the right are the corresponding nodes in the schematic view.

• Output Card:

  • Display Options : Screen

    Select all the tick boxes in this section to provide maximum information in the event of failure.

• Device Parameters card:

  • Device Parameters to Match : MOSFET elements : Lengths and widths

    This option allows you to check that transistor sizes on the layout are the same as those on the schematic.

• Merge Devices card:
  • Merge Parallel M (MOSFET) devices [ All ]

    This option allows you to compare layout and schematic where transistors on the layout are placed in parallel in order to give a greater drive strength. This option is essential for any circuit including the BIM_BUF buffer cell which uses this parallel MOSFET technique.

  • Merge Series MOSFETs [ All ]

    This option allows you to compare layout and schematic where series transistors are not in the same order (e.g. nand3 schematic contains three series NMOS transistors, A-B-C, while layout contains three series NMOS transistors, A-C-B). Such circuits are functionally identical. Since this option precludes the checking of transistor sizes, you should use it sparingly and correct any such discrepancies in transistor ordering when they are found (this often involves changing the schematic to match the layout).

• Parasitics card:
  • Remove Capacitors

    Schematic netlists do not usually contain parasitic capacitors such as those found in layout netlists. For a successful LVS you should select the Remove Capacitors option and set the threshold for removal at a very large value so that all capacitors are ignored. For capacitors 1 (Farrad) is a suitably large value.