Netlist File

 # Please note that the magic router is very fussy about the format of this
 # file. Spaces are important; any line beginning with a space is ignored;
 # if a space is included at the end of a terminal name the routing will fail.
 # Type "man -s 5 net" for further details.

 # divider.net
 #
 #
 # This file assumes two sub-modules: control (instance name control_0) and
 # datapath  (instance name datapath_0)
 # It also assumes bus signals (Operand1, Operand2, Quotient, Remainder) use square brackets
 # for index values
 # The control and feedback signals listed are those for a Type#1 divider
 #
 # If your design does not match these assumptions then you will have to edit
 # this file

 # The required labels within datapath are:
 #   Vdd!
 #   GND!
 #   Clock
 #   nReset
 #   Test
 #   SDI
 #   SDO
 #   Operand1[0]
 #   Operand1[1]
 #   Operand1[2]
 #   Operand1[3]
 #   Operand1[4]
 #   Operand1[5]
 #   Operand1[6]
 #   Operand1[7]
 #   Operand2[0]
 #   Operand2[1]
 #   Operand2[2]
 #   Operand2[3]
 #   Operand2[4]
 #   Operand2[5]
 #   Operand2[6]
 #   Operand2[7]
 #   Quotient[0]
 #   Quotient[1]
 #   Quotient[2]
 #   Quotient[3]
 #   Quotient[4]
 #   Quotient[5]
 #   Quotient[6]
 #   Quotient[7]
 #   Remainder[0]
 #   Remainder[1]
 #   Remainder[2]
 #   Remainder[3]
 #   Remainder[4]
 #   Remainder[5]
 #   Remainder[6]
 #   Remainder[7]
 #   Subtract
 #   Increment
 #   LoadC
 #   LoadD
 #   LoadACC
 #   LoadQ
 #   LoadR
 #   EnableOp1
 #   EnableOp2
 #   EnableACC
 #   EnableD
 #   Overflow
 #   nBorrow


 # The required labels within control unit are:
 #   Vdd!
 #   GND!
 #   Clock
 #   nReset
 #   Test
 #   SDI
 #   SDO
 #   Req
 #   Done
 #   Subtract
 #   Increment
 #   LoadC
 #   LoadD
 #   LoadACC
 #   LoadQ
 #   LoadR
 #   EnableOp1
 #   EnableOp2
 #   EnableACC
 #   EnableD
 #   Overflow
 #   nBorrow


 #
 # Core power and ground pads:
 # (These should be wired first by hand to ensure that wide enough metal tracks
 # are used)
 #
 # For input pads:
 #   OEN signals are pulled high to disable output behaviour
 #   IE signals are pulled high to enable input behaviour
 #   I signals are pulled high to stop them from floating
 #
 # For output pads:
 #   OEN signals are pulled low to enable output behaviour
 #   IE signals are pulled low to disable input behaviour
 #
 # For all pads:
 #   PE signals are pulled low to disable pull-down behaviour
 #   DS signals are pulled low to contol slew rate
 #

datapath_0/Vdd!
control_0/Vdd!
VDDcore/Vdd!
Clock/OEN
nReset/OEN
Test/OEN
SDI/OEN
Req/OEN
Operand1_0/OEN
Operand1_1/OEN
Operand1_2/OEN
Operand1_3/OEN
Operand1_4/OEN
Operand1_5/OEN
Operand1_6/OEN
Operand1_7/OEN
Operand2_0/OEN
Operand2_1/OEN
Operand2_2/OEN
Operand2_3/OEN
Operand2_4/OEN
Operand2_5/OEN
Operand2_6/OEN
Operand2_7/OEN
Clock/IE
nReset/IE
Test/IE
SDI/IE
Req/IE
Operand1_0/IE
Operand1_1/IE
Operand1_2/IE
Operand1_3/IE
Operand1_4/IE
Operand1_5/IE
Operand1_6/IE
Operand1_7/IE
Operand2_0/IE
Operand2_1/IE
Operand2_2/IE
Operand2_3/IE
Operand2_4/IE
Operand2_5/IE
Operand2_6/IE
Operand2_7/IE
Clock/I
nReset/I
Test/I
SDI/I
Req/I
Operand1_0/I
Operand1_1/I
Operand1_2/I
Operand1_3/I
Operand1_4/I
Operand1_5/I
Operand1_6/I
Operand1_7/I
Operand2_0/I
Operand2_1/I
Operand2_2/I
Operand2_3/I
Operand2_4/I
Operand2_5/I
Operand2_6/I
Operand2_7/I

datapath_0/GND!
control_0/GND!
VSScore/GND!
SDO/OEN
Done/OEN
Quotient_0/OEN
Quotient_1/OEN
Quotient_2/OEN
Quotient_3/OEN
Quotient_4/OEN
Quotient_5/OEN
Quotient_6/OEN
Quotient_7/OEN
Remainder_0/OEN
Remainder_1/OEN
Remainder_2/OEN
Remainder_3/OEN
Remainder_4/OEN
Remainder_5/OEN
Remainder_6/OEN
Remainder_7/OEN
SDO/IE
Done/IE
Quotient_0/IE
Quotient_1/IE
Quotient_2/IE
Quotient_3/IE
Quotient_4/IE
Quotient_5/IE
Quotient_6/IE
Quotient_7/IE
Remainder_0/IE
Remainder_1/IE
Remainder_2/IE
Remainder_3/IE
Remainder_4/IE
Remainder_5/IE
Remainder_6/IE
Remainder_7/IE
SDO/PE
Done/PE
Quotient_0/PE
Quotient_1/PE
Quotient_2/PE
Quotient_3/PE
Quotient_4/PE
Quotient_5/PE
Quotient_6/PE
Quotient_7/PE
Remainder_0/PE
Remainder_1/PE
Remainder_2/PE
Remainder_3/PE
Remainder_4/PE
Remainder_5/PE
Remainder_6/PE
Remainder_7/PE
Clock/PE
nReset/PE
Test/PE
SDI/PE
Req/PE
Operand1_0/PE
Operand1_1/PE
Operand1_2/PE
Operand1_3/PE
Operand1_4/PE
Operand1_5/PE
Operand1_6/PE
Operand1_7/PE
Operand2_0/PE
Operand2_1/PE
Operand2_2/PE
Operand2_3/PE
Operand2_4/PE
Operand2_5/PE
Operand2_6/PE
Operand2_7/PE
SDO/DS
Done/DS
Quotient_0/DS
Quotient_1/DS
Quotient_2/DS
Quotient_3/DS
Quotient_4/DS
Quotient_5/DS
Quotient_6/DS
Quotient_7/DS
Remainder_0/DS
Remainder_1/DS
Remainder_2/DS
Remainder_3/DS
Remainder_4/DS
Remainder_5/DS
Remainder_6/DS
Remainder_7/DS
Clock/DS
nReset/DS
Test/DS
SDI/DS
Req/DS
Operand1_0/DS
Operand1_1/DS
Operand1_2/DS
Operand1_3/DS
Operand1_4/DS
Operand1_5/DS
Operand1_6/DS
Operand1_7/DS
Operand2_0/DS
Operand2_1/DS
Operand2_2/DS
Operand2_3/DS
Operand2_4/DS
Operand2_5/DS
Operand2_6/DS
Operand2_7/DS

 #
 # Input pads:
 #

datapath_0/Clock
control_0/Clock
Clock/C

datapath_0/nReset
control_0/nReset
nReset/C

datapath_0/Test
control_0/Test
Test/C

datapath_0/SDI
SDI/C

control_0/Req
Req/C

datapath_0/Operand1[0]
Operand1_0/C

datapath_0/Operand1[1]
Operand1_1/C

datapath_0/Operand1[2]
Operand1_2/C

datapath_0/Operand1[3]
Operand1_3/C

datapath_0/Operand1[4]
Operand1_4/C

datapath_0/Operand1[5]
Operand1_5/C

datapath_0/Operand1[6]
Operand1_6/C

datapath_0/Operand1[7]
Operand1_7/C

datapath_0/Operand2[0]
Operand2_0/C

datapath_0/Operand2[1]
Operand2_1/C

datapath_0/Operand2[2]
Operand2_2/C

datapath_0/Operand2[3]
Operand2_3/C

datapath_0/Operand2[4]
Operand2_4/C

datapath_0/Operand2[5]
Operand2_5/C

datapath_0/Operand2[6]
Operand2_6/C

datapath_0/Operand2[7]
Operand2_7/C

 #
 # Output pads:
 #

control_0/SDO
SDO/I

control_0/Done
Done/I

datapath_0/Quotient[0]
Quotient_0/I

datapath_0/Quotient[1]
Quotient_1/I

datapath_0/Quotient[2]
Quotient_2/I

datapath_0/Quotient[3]
Quotient_3/I

datapath_0/Quotient[4]
Quotient_4/I

datapath_0/Quotient[5]
Quotient_5/I

datapath_0/Quotient[6]
Quotient_6/I

datapath_0/Quotient[7]
Quotient_7/I

datapath_0/Remainder[0]
Remainder_0/I

datapath_0/Remainder[1]
Remainder_1/I

datapath_0/Remainder[2]
Remainder_2/I

datapath_0/Remainder[3]
Remainder_3/I

datapath_0/Remainder[4]
Remainder_4/I

datapath_0/Remainder[5]
Remainder_5/I

datapath_0/Remainder[6]
Remainder_6/I

datapath_0/Remainder[7]
Remainder_7/I

 #
 # Internal Scan Path:
 #

datapath_0/SDO
control_0/SDI

 #
 # Control Signals:
 #

control_0/Subtract
datapath_0/Subtract

control_0/Increment
datapath_0/Increment

control_0/LoadC
datapath_0/LoadC

control_0/LoadD
datapath_0/LoadD

control_0/LoadACC
datapath_0/LoadACC

control_0/LoadQ
datapath_0/LoadQ

control_0/LoadR
datapath_0/LoadR

control_0/EnableOp1
datapath_0/EnableOp1

control_0/EnableOp2
datapath_0/EnableOp2

control_0/EnableACC
datapath_0/EnableACC

control_0/EnableD
datapath_0/EnableD


 #
 # Feedback Signals:
 #

control_0/Overflow
datapath_0/Overflow

control_0/nBorrow
datapath_0/nBorrow


 #
 # End of netlist