module divider(
  output wire [7:0] Quotient, Remainder,
  output wire       Done, SDO,
  input       [7:0] Operand1, Operand2,
  input             Req, Clock, nReset, Test, SDI
  );

timeunit 1ns;
timeprecision 100ps;

// include netlist information from divider.vnet

`include "divider.vnet"

endmodule