Integrated Circuit Engineering 2

E-Mail File Submission

Design submission e-mails should be sent to I.McNally@elec.canterbury.ac.nz and timestamped on arrival no later than 2pm on Monday 12th May.

The text of your e-mail must:

1. Have a subject line: TEAM XXX Design Submission
2. List all team members involved in the creation of the design.
3. List all submitted files.
4. Identify which of the following stages have been completed:

   	Passed	Failed	Not Attempted
   XXX_DESIGN Layout DRC
   XXX_DESIGN Layout SLS simulation
   XXX_DESIGN Layout T-Spice timing simulation
   XXX_DESIGN Schematic T-Spice simulation
   XXX_DESIGN Layout versus Schematic check

The following files should be attached to your e-mail:

• XXX_DESIGN.tdb
• XXX_DESIGN.sdb
• XXX_DESIGN.out
• XXX_DESIGN.results

Details of these files are as follows:

• XXX_DESIGN.tdb

  L-Edit library file for your multiplier

  • The top level cell must be named "XXX_DESIGN"
    The top level cell should be design rule correct.
  • ALL cells must have names beginning "XXX_"
  • A library cell "XXX_LIB" must be included. This cell includes one instance each of ALL leaf cells used.
  • All extraneous cells must be deleted before submission.

• XXX_DESIGN.sdb

  S-Edit library file for your multiplier

  • The top level cell must be named "XXX_DESIGN"
  • ALL cells must have names beginning "XXX_" with the exception of NMOS/PMOS/Vdd/GND.
  • A library cell "XXX_LIB" must be included. This cell includes one symbol each for ALL leaf cells used.
  • All extraneous cells must be deleted before submission.

• XXX_DESIGN.out

  LVS output file for the top level cells.

  To help you with the LVS task a couple of files have been created:

  • XXX_DESIGN.vdb LVS configuration file
  • MULTIPLY.pre prematch file

  XXX_DESIGN.vdb configures LVS to compare XXX_DESIGN.spc layout netlist with XXX_DESIGN.sp schematic netlist using the prematch file MULTIPLY.pre which lists all inputs and outputs for the multiplier design.

  To run the final LVS check you should copy the two files into your own user space and open the XXX_DESIGN.vdb file using LVS. You will then have to modify the configuration to compare the your own layout and schematic netlists. If you find that the LVS fails, you may relax the checking options as follows:

  • Merge Serial MOSFETs

    You will need this option where the order of series transistors is not the same in the schematic and netlist. This may happen where the order of transistors in a leaf cell is not the same in the schematic and netlist but may also happen where the order of connections to a gate within a module is not the same. See the web document, Advice on LVS options, for more details.

  • Don't Match Device Parameters : MOSFET elements : Lengths and widths

    You will need to turn off device parameter matching if you have not set the length and width values of transistors in the schematic leaf cells. See the web document, Advice on LVS options, for more details.

  The file "XXX_DESIGN.out" will be created when the LVS is run. It is this file that you must submit.

• XXX_DESIGN.results

  SLS simulation output file

  To help with final sls simulation, a couple of simulation stimulus files are available:

  • multicycle.cmd
  • pipeline.cmd

  Both files perform 256 multiplications (0x0 0x1 ..... 15x14 15x15). In the case of multicycle.cmd, new operands are presented once every 6 clock cycles. This should be suitable for all designs. In the case of pipeline.cmd, new operands are presented every clock cycle. This should be suitable for all single cycle designs and pipeline designs.

  To run a simulation with one of these files you would copy the file into your unix user space (i.e. save it under \\rockhopper\<username>\ ) and then run a unix simulation command like:

      spacesls -cmd pipeline.cmd XXX_DESIGN.gds XXX_DESIGN
  

  See the web document, Switch Level Simulation of L-Edit Designs, for more details.

  Note that these are very simple stimulus files. A design which gives the correct results with these stimulus files does not necessarily meet the design specification.

  Since there are 256 results to be checked you really need to post-process the output from such a simulation. For this reason, a new script "finalsls" has been provided:

      finalsls XXX_DESIGN.gds XXX_DESIGN
  

  When this command is run it invokes the "spacesls" script using the multicycle.cmd stimulus. After the waveforms are displayed you should close the waveform window (File -> Exit). The post processing will then commence, checking each answer against the expected result. The output from this checking will go to the screen and to a file called "XXX_DESIGN.results" which is the file that you should submit.

Please take time to read this document carefully. Marks will be deducted where any of the deliverables listed above are missing or not as specified.

Fabrication

If the one or other of the "XXX_DESIGN.tdb" and "XXX_DESIGN.results" files is not as specified the design will not be fabricated.

Note that it is not a prerequisite that the design passes all the test vectors in order to be fabricated, it is merely required that the cell names are correct, that the design passes the DRC and that a simulation is possible.

Plot of Top Cell

In addition to your e-mail you should also submit a printout of your top cell to facilitate the error checking procedure. A single page plot marked with your team name and posted into pigeon hole number 7 is sufficient.