Integrated Circuit Engineering 2

Notes 2003

The following lecture notes are available

• Introduction
• CMOS
• Cell Design and Euler Paths
  • Taps
• System Design using Standard Cells
• Gate Matrix and Bitslice Design
• Storage
  • extras
• Clock Distribution
• Alternative Design Styles
• PLAs, ROMs and RAMs
• Input / Output
• Design Flows and Design Automation

Printable postscript copies of these notes are available:

• Landscape notes 4 to a page

Assignment and Lab Info 2003

• Assignment 1 - Full Custom CMOS Design
  • Documentation for Initial Cell Library
    • Stick Diagrams for Initial Cell Library
  • Specification of a 4 bit multiplier
    • Multiplier Design
    • Adder Design
  • E-Mail File Submission

• Lab 1   L-Edit - Thursday 27th February 4.10pm CAE-2

  • MOSIS SCMOS Design Rules (simplified local version)
  • Stick Diagram Colour Code

• Lab 2   S-Edit - Thursday 11th March 4.10pm CAE-2

  • Advice on LVS options

• Lab 3   Space - Thursday 3rd April 4.10pm CAE-2

  • Switch Level Simulation of L-Edit Designs

UoC Tiny Chip Info 2003

• UoC Tiny Chip
• Documentation for Initial Cell Library
  • Stick Diagrams for Initial Cell Library

Links to other pages

• MOSIS SCMOS Design Rules
• International Technology Roadmap for Semiconductors
  These predictions explain why Moore's law holds.

Iain McNally

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