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The University of Southampton

ELEC6236 Digital System Design

Module Overview

The following topics will be covered: - How SystemVerilog is interpreted for simulation and synthesis - How to use EDA tools to configure FPGAs - The principles of functional verification of digital systems - The principles of Built-In Self-Test and system-level design for test techniques. - The module will introduce you to the industry-standard hardware description language System Verilog (and to SystemC).

Aims and Objectives

Learning Outcomes

Knowledge and Understanding

Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:

  • Describe sequential digital systems in a hardware description language.
  • How to include design for test structures in a sequential digital system
Subject Specific Intellectual and Research Skills

Having successfully completed this module you will be able to:

  • Know how to model circuits and systems in SystemVerilog.
  • Generate tests for a combinational digital circuit
Subject Specific Practical Skills

Having successfully completed this module you will be able to:

  • Validate a digital system using a simulator
  • Synthesise a digital system to an FPGA


- Hardward Description Languages: SystemVerilog - Basic building blocks and language constructs - Register Transfer-Level Design - Controller/datapath partitioning - Synthesising designs to FPGAs - Simulation and synthesis principles - Test generation and design for test - Built in Test: Principles, structures, signature analysis - Multiple Clock Domains: Transferring data between clock domains.

Learning and Teaching

Follow-up work15
Supervised time in studio/workshop6
Wider reading or practice55
Completion of assessment task19
Preparation for scheduled sessions15
Total study time150


Assessment Strategy

Laboratory sessions are scheduled in the labs on level 2 of the Zepler building Length of each session: 3 hours Number of sessions completed by each student: 1 Max number of students per session: unlimited Demonstrator:student ratio: 1:12 Preferred teaching weeks: 6 to 7


MethodPercentage contribution
Continuous Assessment 30%
Final Assessment  70%


MethodPercentage contribution
Set Task 100%


MethodPercentage contribution
Set Task 100%

Repeat Information

Repeat type: Internal & External

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