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Digital Systems Synthesis

When you'll study it
Semester 2
CATS points
15
ECTS points
7.5
Level
Level 7
Module lead
Tomasz Kazmierski
Academic year
2021-22

Module overview

Describe the design of complex digital systems using a (SystemVerilog and SystemC based) behavioural synthesis approach.

Provide understanding of the algorithms which underpin behavioural synthesis including scheduling, allocation and binding.

Gain hands-on experience in the application of behavioural synthesis to generate designs optimised for user-defined constraints.

Describe digital design for testability techniques at the behavioural and RTL levels.

Provide an overview of emerging SoC design and test methods.

Describe system level low power design methods.

The module will use the hardware description language SystemVerilog (and also SystemC), introduced in ELEC6236 Digital System Design.

Linked modules

Pre-requisites: ELEC3221 OR COMP6238

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