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The University of Southampton

ELEC6233 Digital Systems Synthesis

Module Overview

Describe the design of complex digital systems using a (SystemVerilog and SystemC based) behavioural synthesis approach. Provide understanding of the algorithms which underpin behavioural synthesis including scheduling, allocation and binding. Gain hands-on experience in the application of behavioural synthesis to generate designs optimised for user-defined constraints. Describe digital design for testability techniques at the behavioural and RTL levels. Provide an overview of emerging SoC design and test methods. Describe system level low power design methods. The module will use the hardware description language SystemVerilog (and also SystemC), introduced in ELEC6236 Digital System Design.

Aims and Objectives

Learning Outcomes

Knowledge and Understanding

Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:

  • Advanced digital synthesis techniques including low power techniques, the use of SystemVerilog and SystemC in digital system design
Subject Specific Intellectual and Research Skills

Having successfully completed this module you will be able to:

  • Understand techniques for digital system behavioural synthesis, verification and performance evaluation
Subject Specific Practical Skills

Having successfully completed this module you will be able to:

  • Hands-on experience of optimised behavioural synthesis for user defined constraints, such as power consumption, performance, size
Disciplinary Specific Learning Outcomes

Having successfully completed this module you will be able to:

  • Gain understanding of modern emerging System-on-Chip design methods


Review of hardware description languages and behavioural synthesis of digital systems (SystemVerilog, SystemC, Bluespec). Behavioural synthesis data structures and algorithms - Data and control flow representations - Data flow graph (DFG) descriptions - Control data flow graph (CDFG) descriptions - Extended Petri-net models Synthesis and design space - Design space exploration - Constructive vs. transformational/iterative techniques - Behavioural optimisation - Scheduling, allocation, module binding and controller synthesis Scheduling and binding algorithms - Unconstrained and constrained scheduling - Scheduling of multicycled and pipelined functional modules - Allocation and binding algorithms - Interconnect allocation and optimisation - Overview of transformational/iterative approaches (simulated annealing, genetic algorithms) Design for testability - Design for Testability: scan-based and built-in-self-test (BIST) techniques - Test scheduling, test controllers, on-line test Low power design of IP core for SoC applications, development of a high-level synthesis system.

Learning and Teaching

Preparation for scheduled sessions18
Wider reading or practice34
Completion of assessment task22
Follow-up work18
Total study time150

Resources & Reading list

Giovanni De Micheli. Synthesis and optimisation of digital circuits. 

Black, D.C., Donovan, J., SystemC (2004). from the Ground Up. 

Mark Zwolinski. Digital system design with VHDL. 

Sabih Gerez. Algorithms for VLSI design automation. 

John P Elliott. Understanding behvioural synthesis. 

SystemC Quick Reference Guide. 

Andrew Rushton. VHDL for logic synthesis. 

Gajski, D.D., Abdi, S., Gerstlauer, A., Schirner, G (2009). Embedded System Design. 

Zwolinski M (2009). Digital System Design with SystemVerilog. 


Assessment Strategy

Laboratory sessions are scheduled in the labs on level 2 of the Zepler building Length of each session: 15 minutes Number of sessions completed by each student: 1 Max number of students per session: 8 Demonstrator:student ratio: 1:1 Preferred teaching weeks: 10 to 11


MethodPercentage contribution
Continuous Assessment 50%
Final Assessment  50%


MethodPercentage contribution
Set Task 100%


MethodPercentage contribution
Set Task 100%

Repeat Information

Repeat type: Internal & External

Linked modules

Pre-requisites: ELEC3221 OR COMP6238

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