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Digital System Design

When you'll study it
Semester 1
CATS points
15
ECTS points
7.5
Level
Level 7
Module lead
Mark Zwolinski
Academic year
2021-22

Module overview

The following topics will be covered:

  • How SystemVerilog is interpreted for simulation and synthesis
  • How to use EDA tools to configure FPGAs
  • The principles of functional verification of digital systems
  • The principles of Built-In Self-Test and system-level design for test techniques.
  • The module will introduce you to the industry-standard hardware description language System Verilog (and to SystemC).
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