Until recently design-for-test (DFT) and low power IC design represented two separate research directions. The increasing complexity of modern chips transformed testability and power dissipation into conflicting design objectives. This proposal seeks to bring these two directions together by investigating and developing efficient built-in-self-test (BIST) techniques and architectures that are compatible with low power IC design methods. This proposal aims to investigate in detail some of the promising low power DFT techniques (in particular PC-TSS) that have been recently developed at the University of Southampton. The availability of low power BIST techniques and architectures allow IC designers to address concurrently design and test with the aim of generating self-testable designs that are not only optimised in terms of silicon area but also dissipate less power during test than in functional mode, hence resulting in safer testing. An industrial case study will be used to validate the developed techniques and BIST architectures, including the design and fabrication of a demonstrator chip. The work will be carried out in close collaboration with Philips Semiconductors (UK), and University of Iowa (USA).
Collaborating research institutes, centres and groups
Sudhakar M. Reddy,
Janusz Rajski,, 2006
Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction
& Nicola Nicolici, 2004 , IEEE Transactions on Computer-Aided Design , 23 (7) , 1142--1153