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Professor Peter Ashburn BSc, PhD, CEng, FIET, MIEEE, MIOP

Professor in the Nano Group of ECS

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Professor Peter Ashburn is part of the Institute for Life Sciences at the University of Southampton.

Born in Rotherham, Yorkshire, I studied for my bachelor and doctoral degrees in electrical and electronic engineering at the University of Leeds, England, graduating in 1974. I have always been fascinated by the interactions at the interface between industrial and university research, and this fascination is an important motivation for my research.

My career began at the Philips Research Labs, where I gained valuable experience of silicon bipolar and MOS technology and electron beam lithography. After moving to the University of Southampton as a lecturer, I worked on polysilicon emitters in collaboration with Plessey. This work led to the development of a self-aligned, double polysilicon bipolar technology that is still in production today. The next phase of my career was a series of research projects on the applications of low temperature silicon epitaxy and silicon-germanium epitaxy, which led to work on SiGe heterojunction bipolar transistors. This research theme has been very fruitful and highly collaborative, involving extensive interactions with British Telecom, Zarlink, Centre National d’Etudes des Telecommunications, and ST Microelectronics.

As channel lengths of MOS transistors move to nanometer dimensions, it is clear that major innovations will be needed to the architecture of MOS transistors. To control short channel effects, technologies will be needed for double gates, raised sources and drains, surround gates, vertical channels and ultimately 3D integrated structures and hence my research team is actively pursuing these possibilities. As part of this research, I have managed the European Union SIGMOS project, which had the goals of producing 50nm MOSFETs with raised sources & drains, SiGe p-channels, and strained silicon n-channels using Si:C and low capacitance vertical MOSFETs. These topics were pursued through the European Union SINANO project and are currently being pursued through a UK-funded project on vertical MOSFETs for RF applications.

I am currently a professor in the Nano Group of the School of Electronics and Computer Science. I have published over 250 academic papers and have written two text books.

Research interests

Innovations in nanoelectronics technology often arise through new developments in physics and materials science, SiGe technology being a perfect example. My research team is therefore continuing to do basic research in physics and materials science for application in new types of silicon electronic device. My current research interests cover the following projects:

  1. Surround gate vertical MOSFETs: we are developing novel architectures for vertical MOSFETs for reducing overlap capacitance and suppressing short-channel effects. Application of vertical MOSFETs in radio frequency circuits is being researched.
  2. Transistor-in-a-grain technology for ultimate CMOS: we have developed a self-aligned amorphous silicon crystallization technique using a germanium seed and are researching the use of this technique to place small geometry MOS transistors inside a grain of polycrystalline silicon.
  3. Vacancy engineering for boron diffusion suppression: we are using vacancy-fluorine clusters to suppress boron diffusion in silicon and have applied this technique to silicon bipolar technology to achieve a world record cut-off frequency of 110GHz.
  4. Behaviour of fluorine in silicon: our earlier research has shown that fluorine has a variety of interesting and useful properties in silicon. We are currently using fluorine to dramatically increase the crystallization distance during metal induced lateral crystallization of amorphous silicon for application in thin film transistors used in displays.
  5. Silicon compatible carbon nanotube growth: we are researching a metal-free carbon nanotube growth method which is fully compatible with CMOS. The method uses germanium nanoparticles to seed the nanotube growth and yields single-wall, defect-free carbon nanotubes, with diameters typically less than 2nm.
  6. Carbon nanotube FETs: our new carbon nanotube growth method is currently being applied to the fabrication of carbon nanotube field effect transistors.
  7. Silicon nanowire transistors for biosensing applications.

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Book Chapter



Professor Peter Ashburn
University of Southampton SO17 1BJ

Room Number: 53

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