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The University of Southampton

ELEC2221 Digital Systems and Signal Processing

Module Overview

This module is taught by a combination of lectures, laboratory exercises and a design assignment. You will gain practical knowledge of digital system design and of digital signal processing in the context of modern systems. The design exercise is intended to synthesise both sides of the module content, so as to broaden and deepen understanding.

Aims and Objectives

Module Aims

To introduce techniques of designing robust, testable sequential digital systems, writing and debugging synthesisable modules in a hardware description language (SystemVerilog) and verifying the functionality of those modules by simulation. To provide practical experience in the design and diagnosis of sequential digital systems. To introduce concepts of stochastic signals, and to develop understanding of sampling, quantisation and coding in a signal processing setting oriented towards communications.

Learning Outcomes

Knowledge and Understanding

Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:

  • Sequential digital system design for implementation in CPLDs and FPGAs
  • The principles of Design for Test and apply them in practice
  • Stochastic signals and their signal processing in communication systems, including sampling, quantisation and coding
Subject Specific Intellectual and Research Skills

Having successfully completed this module you will be able to:

  • Describe state machines of moderate complexity in SystemVerilog, simulate and synthesise into hardware
  • Design testbenches to verify your design
  • Build and debug a digital circuit
  • Develop CPLD and FPGA implementations of combinational and sequential digital systems
  • Develop working knowledge of state-of-the-art commercial software tools for digital system design
  • Understand the the characteristics of stochastic signals and the ideas of sampling, quantisation and coding within the context of communications signals
  • Create a digital representation of an analogue signal, which is suitable for use in communication systems
  • Compress the digital representation of an analogue signal and protect it from transmission errors
Transferable and Generic Skills

Having successfully completed this module you will be able to:

  • Present results of design work in a formal report
  • Address novel design challenges by choosing appropriate analysis and design methods


Communications part (14 lectures): Characterisation of Stochastic Signals - Probability and cumulative density functions (PDF / CDF), auto- and cross-correlation, power spectral density, stochastic quantities and filtering Sampling and Quantisation: - Analogue-to-digital conversion - Sampling: Nyquist criterion, frequency domain - Aliasing - Baseband and bandpass sampling - Quantisation and signal-to-noise ratio - Digital-to-analogue conversion - Reconstruction filtering Source and channel coding Digits (22 lectures): - Analysis and Design of Synchronous State Machines - RTL synthesis of standard Combinational and Sequential Building Blocks - Introduction to SystemVerilog assertion-based verification - Software tools for CPLD and FPGA synthesis - Implementation of Basic Microprocessor-Core Blocks: Registers, ALU, SRAM, IO ports, Instruction Decoder Synthesis of a simplified MIPS microprocessor on FPGA - Design for Testability: Testing combinational and sequential digital systems Boundary Scan Build-in self-test

Learning and Teaching

Preparation for scheduled sessions18
Completion of assessment task13
Wider reading or practice43
Follow-up work18
Total study time140

Resources & Reading list

J F Wakerly (2006). Digital Design - Principles and Practices. 

M M Mano, M D Ciletti, Digital Design (2007). Digital Design. 

Laboratory space and equipment required. CPLD and FPGA development kits

M. Zwolinski (2010). Digital System Design with SystemVerilog. 

Software requirements. Modelsim, ispLever, Synplify, Altera Quartus

Zwolinski M (2004). Digital System Design with VHDL,. 

I. Otung (2001). Communication Engineering Principles. 



MethodPercentage contribution
Coursework 15%
Examination  (2 hours) 70%
Specialist Laboratory 15%


MethodPercentage contribution
Examination 100%


MethodPercentage contribution
Examination 100%

Repeat Information

Repeat type: Internal & External

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