Module overview
Aims and Objectives
Learning Outcomes
Transferable and Generic Skills
Having successfully completed this module you will be able to:
- Present results of design work in a formal report
- Address novel design challenges by choosing appropriate analysis and design methods
Subject Specific Intellectual and Research Skills
Having successfully completed this module you will be able to:
- Compress the digital representation of an analogue signal and protect it from transmission errors
- Create a digital representation of an analogue signal, which is suitable for use in communication systems
- Understand the the characteristics of stochastic signals and the ideas of sampling, quantisation and coding within the context of communications signals
- Develop working knowledge of state-of-the-art commercial software tools for digital system design
- Develop CPLD and FPGA implementations of combinational and sequential digital systems
- Describe state machines of moderate complexity in SystemVerilog, simulate and synthesise into hardware
- Build and debug a digital circuit
- Design testbenches to verify your design
Knowledge and Understanding
Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:
- Sequential digital system design for implementation in CPLDs and FPGAs
- Stochastic signals and their signal processing in communication systems, including sampling, quantisation and coding
- The principles of Design for Test and apply them in practice
Syllabus
Learning and Teaching
Type | Hours |
---|---|
Wider reading or practice | 48 |
Completion of assessment task | 18 |
Follow-up work | 18 |
Preparation for scheduled sessions | 18 |
Tutorial | 6 |
Lecture | 32 |
Revision | 10 |
Total study time | 150 |
Resources & Reading list
General Resources
Software requirements. Modelsim, ispLever, Synplify, Altera Quartus
Laboratory space and equipment required. CPLD and FPGA development kits
Textbooks
J F Wakerly (2006). Digital Design - Principles and Practices. Pearson Prentice Hall.
I. Otung (2001). Communication Engineering Principles. Palgrave.
Zwolinski M (2004). Digital System Design with VHDL,. Pearson Prentice Hall.
M. Zwolinski (2010). Digital System Design with SystemVerilog. Pearson Prentice Hall.
M M Mano, M D Ciletti, Digital Design (2007). Digital Design. Pearson Prentice Hall.
Assessment
Summative
This is how we’ll formally assess what you have learned in this module.
Method | Percentage contribution |
---|---|
Examination | 70% |
Specialist Laboratory | 15% |
Coursework | 15% |
Referral
This is how we’ll assess you if you don’t meet the criteria to pass this module.
Method | Percentage contribution |
---|---|
Examination | 100% |
Repeat
An internal repeat is where you take all of your modules again, including any you passed. An external repeat is where you only re-take the modules you failed.
Method | Percentage contribution |
---|---|
Examination | 100% |
Repeat Information
Repeat type: Internal & External